Field-Programmable Gate-Array (FPGA) Implementation of Low-Density Parity-Check (LDPC) Decoder in Digital Video Broadcasting – Second Generation Satellite (DVB-S2)

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexitycompared to Turbo-codes has made LDPC codes one of the most popular forward errorcorrection (FEC) codes in most of the recently ratified wireless communication standards.This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratifiedin 2005.In this thesis, the design and architecture of a FPGA implementation of an LDPC decoderfor the DVB-S2 standard are presented. The decoder architecture is an improvement overothers that are published in the current literature. Novel algorithms are devised to usea memory mapping scheme that allows for 360 functional units (FUs) used in decodingto be implemented using the Sum-Product Algorithm (SPA). The functional units (FU)are optimized for reduced hardware resource utilization on a FPGA with a large numberof configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-checkmodule (PCM) is presented that verifies the parity-check equations of the LDPC codes.Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standardand their influence on the decoder design is discussed.Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for twoFPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a XilinxVirtex-6 family FPGA is used to demonstrate the portability of the design. The synthesisresults show that the hardware resource utilization and minimum throughput of the decoderspresented are competitive with a DVB-S2 LDPC decoder found in the current literature thatalso uses FPGA technology.